[Saam]

GDB Topic

Flip-flops are the sequential logic circuits which unlike the combinational circuits have the capability to store their previous state. Due to their storage ability, these flip-flops are used as the basic building blocks in the design of memory elements such as registers. To work as a memory unit, multiple flip-flops are connected together in a specific arrangement. Two of the most common flip-flop arrangements are Master-Slave Flip-flop Pairs and Pulse-Triggered Flip-flops.

If you want to design the memory unit for an embedded microprocessor, which of the two flip-flop arrangements would you chose in this situation to ensure high performance?

Give your opinion as brief and precise as possible.

[Prince]

GDB Topic

Flip-flops are the sequential logic circuits which unlike the combinational circuits have the capability to store their previous state. Due to their storage ability,these flip-flops are used as the basic building blocks in the design of memory elements such as registers. To work as a memory unit, multiple flip-flops are connected together in a specific arrangement. Two of the most common flip-flop arrangements are Master-Slave Flip-flop Pairs and Pulse-Triggered Flip-flops.

If you want to design the memory unit for an embedded microprocessor, which of the two flip-flop arrangements would you chose in this situation to ensure high performance?

Give your opinion as brief and precise as possible.

solution ????

[Saam]

prince g solution e chahiye h....

[Muhammad Abrar Khan]

Solution Idea Not a Final Answer CS302
Pulse-triggered flip-flops are widely used in microprocessors in recent years due to their high performance. JK flip-flops are more powerful than D flip-flops. However, designs of pulse-triggered JK flip-flops are seldom mentioned. Generally, JK flip-flops are designed on the basis of D flip-flops, and have more power consumption and larger delay than D flipflops. An explicit-pulsed double-edge triggered JK flip-flop (ep-DET-JKFF) is proposed, which is designed directly based on the characteristics of JK flip-flops and pulse-triggered flip-flops directly. Simulation using HSPICE and a 0.18 ¿m technology shows that the proposed pulsed JK flip-flop has low power dissipation and small delay comparable to those of published pulsed D flip-flop, and has improvement of 11.4%~32.9% in transistor count, 44.1% in delay and 42.3%~55.9% in PDP (Product of Power and Delay), as compared to the pulsed JK flipflop based on pulsed D flip-flops.